With the rising level of integration in semiconductor devices such as semiconductor integrated circuits and multilayer wiring devices and with higher device densities, line spacings have become narrower, leading to the problem of wire delay due to increased capacitance between lines.
Although increases in power consumption due to leakage currents in wiring layer insulating films have hitherto been known, in generations of semiconductor devices having line spacings greater than 1 μm, the influence of such leakage currents on the overall device has been small. However, at line spacings not greater than 1 μm, owing to the tight dimensions of the spacing and the increase in the scale of the wiring, such leakage currents have a greater influence on power consumption. In particular, as circuits come to be formed at line spacings not greater than 0.1 μm, the leakage current between lines will exert a large influence on the characteristics and life of the device.
The wire delay T is affected both by the line resistance and the capacitance between lines. Letting the line resistance be R and the capacitance between lines be C, the wire delay is the quality expressed asT∞CR.
In this formula, letting the line spacing be D, the electrode surface area (surface area of opposed wiring faces) be S, the dielectric constant of a vacuum be ε0 and the specific dielectric constant of the insulating material provided between the lines be εr, the capacitance C between the lines is expressed asC=ε0εS/D. 
Hence, lowering the dielectric constant of the insulating film is an effective way to make the wire delay smaller.
Currently, to lower the dielectric constant of an insulating film, the multilayer wiring structure of a semiconductor device is often formed of copper lines obtained by electroplating and low-k insulating films (or insulating layers)—also called, depending on the case, etch stoppers, diffusion preventing films or diffusion preventing layers, interlayer insulating films or interlayer insulating layers, etc.—which are formed by spin-on glass (SOG) or plasma chemical vapor deposition (CVD).
However, these insulating films adhere poorly to the copper serving as the wiring material, resulting in film separation at the interface. This is thought to be due to the influence of copper oxide that forms at the surface of the copper with exposure to the atmosphere. Although techniques for removing copper oxide by H2 annealing (heat treatment in a hydrogen-containing atmosphere) or H2 plasma treatment prior to formation of the insulating film are currently in use, film separation continues to be observed. Hence, a satisfactory solution remains to be found (see Patent Document 1).    Patent Document 1: Japanese Patent Application Laid-open No. 2006-303179 (Claims)